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| KESRX04 260 to 470MHz. ASK Receiver with Power Down Preliminary Information DS4997 - 1.5 August 1998 The KESRX04 is a single chip ASK (Amplitude Shift Key) Receiver IC. It is designed to operate in a variety of low power radio applications including keyless entry, general domestic and industrial remote control, RF tagging and local paging systems. The receiver offers an exceptionally high level of integration and performance to meet the local oscillator radiation requirements of regulatory authorities world-wide. Functionally the device works in the same way as the KESRX01 with the added features of low supply voltage, in-band interference rejection (anti-jamming detector), a 2 stage power down to enable receiver systems to be implemented with less than 1mA supply, and a wide IF bandwidth and drive stage to interface to an external ceramic IF band pass filter at intermediate frequencies from 0.2MHz to 15MHz. The KESRX04 is an ideal receiver for difficult reception areas where high level interferers would jam the wanted signal. The anti-jamming circuit allows operation to be possible with interfering signals which are more than 14dB stronger than the wanted signal, without the cost penalties of increased IF selectivity and frequency accuracy. P IFFLT1 IFDC1 IFFLT2 RSSI PIN 1 REF. SPOT IFIN IFDC2 VCC IFOUT VCCRF MIXIP RFOP VEERF RFIN AGC PEAK DATOP DETB PD XTAL1 XTAL2 DF0 DF1 DF2 VCO1 VCO2 VEE LF DSN (9.80/10.01) QP28 Figure 1 Pin Connections (top view) FEATURES s In-band interference rejection (typ. 14dB) s -103dBm Sensitivity (IF BW = 470kHz) s AGC around LNA and Mixer s Low supply voltage (3 to 6V) s 2 stage power-down for low current applications s Interface for ceramic IF filters up to 15MHz APPLICATIONS s Remote Keyless Entry s Security, tagging s Remote Controlled equipment ORDERING INFORMATION KESRX04/IG/QP1S (anti-static tubes) KESRX04/IG/QP1T (tape and reel) ABSOLUTE MAXIMUM RATINGS Supply Voltage Vcc Storage temperature,Tstg Junction Temperature, Tj RF Input power -0.5V to +7V -55 to 150C -55 to 150C +20dBm from 50 agc RF Input mixer Ceramic IF Filter RSSI detector Anti-jam data filter Slicer SAW Filter LNA Noise reduction Filter Local Oscillator Sliced data Ref Figure 2 Typical system application KESRX04 PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol IFFLT1 IFDC1 IFIN IFDC2 VCC IFOUT VCCRF MIXIP RFOP VEERF RFIN AGC PEAK DATOP DSN LF VEE VCO2 VCO1 DF2 DF1 DF0 XTAL2 XTAL1 PD DETB RSSI IFFLT2 Function Noise reducing IF filter Log amp dc stability capacitor Log amp input Log amp dc stability capacitor Positive supply IF output to external IF filter Positive supply for RF circuits Mixer input Output from LNA Negative supply for RF circuits Input to LNA RF AGC time constant Data signal peak detect Sliced data output Data slice level PLL loop filter Negative supply Voltage controlled oscillator Voltage controlled oscillator Data filter Data filter Data filter Crystal oscillator Crystal oscillator Power down Anti-jam detector input RSSI output Noise reducing IF filter DESCRIPTION The single-conversion super-heterodyne receiver approach is now generally considered the way forward for ISM band type applications because of lower cost, superior selectivity, lower radiation, and flexibility over other techniques. For powerconscious, hand-held applications KESRX04 provides improved performance and flexibility on a lower 3.0V supply and a power-down feature allows faster switch-on times for use in a pulsed power saving mode. Although this is a relatively simple receiver, the flexibility of using an external IF filter allows the designer to choose both the selectivity and the IF in order to optimise the performance for a wide range of applications and locations world wide. The KESRX04, with its Anti-jamming detector circuit, is an ideal ASK / OOK receiver for difficult reception areas caused by interference such as "Amateur Radio Repeater Stations" and Wireless Stereo Head-Phones". Operation is possible with interfering signals which are more than 14dB stronger that the wanted signal (IF bandwidth = 470kHz.), without the cost penalities of increased IF selectivity and frequency accuracy. Figure 2 is the system block diagram for the device with an external ceramic IF filter, SAW fillter and noise reduction filter. 2 KESRX04 ELECTRICAL CHARACTERISTICS Test conditions T amb = -40C to + 85C, VCC = 3.0V to 6.0V. These characteristics are guaranteed by either device characterisation, production test and or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated using test circuit Figure 12. Characteristic Supply voltage Ambient temperature Test Frequency local Oscillator Symbol VCC Ta Min 3.0 -40 470 480.7 Value Typ Max 6.0 +85 Units V C MHz MHz local oscillator frequency configured for high side injection, except where otherwise specified Conditions ESD Protection: All pins meet 2kV Human Body Model requirement. Except pins 9 and 11, which are limited to 700V and pins 18 and 19 which are limited to 1.00kV. ELECTRICAL CHARACTERISTICS D.C. T amb = -40C to + 85C, VCC = 3.0V to 6.0V. These characteristics are guaranteed by either device characterisation production test and or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Parameter Supply Current Receive mode (PD2) Power down (PD1) Icc Icc1 3.7 0.33 4.5 0.5 mA mA All. PD=High. RF input <-50dBm. All. PD=Vcc/2 or high impedance source. Vcc = 3 to 6.0V (4) Power down (PD0) Icc2 33 50 A All. PD=low Symbol Min Value Typ Units Max Condition ELECTRICAL CHARACTERISTICS A.C Parameter Input frequency range Intermediate Frequency Sensitivity (test fixture) Sensitivity (application) Symbol Min fs IF Vin(min) Vin(min) 260 0.2 8.0 1.5 Value Typ Max 470 15.0 23.0 MHz MHz. Vrms Vrms All All. (8) 20kB/s data rate at 470MHz. (1) Circuit as Figure 11 with SAW filter removed1kB/s data rate at 433.92MHz. (3) Overload Performance PLL control line (pin 16) To achieve 90% of final value PD0 to PD2 PLL control line (pin 16) To achieve 90% of final value PD1 to PD2 Data output Voltage High Data output Voltage Low Conducted emissions ts3 1.0 3.0 mS Vin(max) ts2 0.5 2.23 2.0 4.0 Vrms mS 20kB/s data rate at 470MHz. (2) All. Circuit as Figure 11 (5) Local Oscillator low side Injection 423.33 MHz. All. Circuit as Figure 11 (5) Local Oscillator low side Injection 423.33 MHz. Ioh=+10A Iol=-10A All Figure 11 (6), local Osc. low side injection = 423.3MHz . Units Condition Voh Vol Antenna (LO) Vcc-0.7V 0.7 5.6 100 Volt Volt Vrms 3 KESRX04 ELECTRICAL CHARACTERISTICS A.C.(continued) These characteristics are typical values measured for a limited sample size. They are not guaranteed by production test. They are only given as a design guide to assist during the design-in phase of KESRX04. Parameter Symbol Value Units Condition Min Anti-jam rejection Typ +14 Max dB Unmodulated interfering signal = -76dBm 433.82MHz. OOK modulated wanted signal = -90dBm 433.92MHz Figure 5 (7) Internal RF Amplifier Parallel input impedance Parallel input impedance Parallel output impedance Parallel output impedance Noise Figure Rfin Rfin Rfout Rfout NF 1.0 // 1.8 1.6 // 1.9 8.8 // 1.7 18 // 1.8 4.5 Noise matching Impedance 1dB compression point (input referred) Rfin 1.0 // 4.6 K // pF Fs=434MHz, Vcc= 5V, Tamb =25C K // pF Fs=315MHz, Vcc= 5V, Tamb =25C K // pF Fs=434MHz, Vcc= 5V, Tamb =25C K // pF Fs=315MHz, Vcc= 5V, Tamb =25C dB Fs=434MHz; Vcc= 5V, Tamb =25C matched 50ohm environment input and output K // nH Fs=434MHz, Vcc= 5V, Tamb =25C dBm Fs=434MHz, Vcc= 5V, Tamb =25C matched 50ohm environment input and output Fs=434MHz., Vcc= 5V, Tamb =25C O/P matched to Mixer input impedance RF Amplifier is conditionally stable Rfin -20 Amplifier gain RFamp 13 dB MIXER Parallel input impedance Parallel input impedance Output impedance Noise Figure (Double side band measurement) MIXIP MIXIP IF1 1.6 // 1.8 1.6 // 1.8 300 K // pF Fs=434MHz, Vcc= 5V, Tamb =25C K // pF Fs=315MHz, Vcc= 5V, Tamb =25C Fs=10.7MHz, Vcc= 5V, Tamb =25C dB Fs=434MHz; Vcc= 5V, Tamb =25C matched 50ohm environment input and output Fs=434MHz., Vcc= 5V, Tamb =25C Measured at input to ceramic filter. Includes 6dB matching loss NF 10 Mixer conversion gain Amix 9 dB IF Strip (RSSI) IF2 input impedance 4.0 K IF=10.7MHz, Vcc= 5V, Tamb =25C IF gain of log amp Alog 80 dB All, Vcc= 5V, Tamb =25C 4 KESRX04 Notes: 1. The Sensitivity of the test fixture Figure 12 is degraded by loading the input to RF amplifier with 50 ohms, lack of image rejection and increasing the data filter bandwidth to 50kHz. Sensitivity is defined as the average signal level measured at the input necessary to achieve a bit error ratio of 0.01 where the input signal is a return to zero pulse at 470MHz.,with an average duty cycle of 50%, 20kB/s data rate with the receiver bandwidth set to 470kHz. Peak RF input level, pin RFIN, to overload the demodulator with the AGC operating. Equivalent to +7dBm for 50 ohm input impedance. Where the input signal is a return to zero pulse at 470MHz. with an average duty cycle of 50%. 20kB/s data rate with the receiver bandwidth set to 470kHz. Sensitivity is defined as the average signal level measured at the input necessary to achieve a bit error ratio of 0.01 where the input signal is a return to zero pulse with an average duty cycle of 50%, 1kB/s data rate. Equivalent to -103dBm for 50ohm input impedance. Does not include insertion loss of SAW filter at RF input but does include IF filter of 470kHz 3dB bandwidth and a data filter bandwidth of 5kHz. This equates closely to a measurement of tangential sensitivity. The performance of the power down option PD1 to PD2 cannot be guaranteed below 3V for temperatures less than 0C Time taken for PLL lock voltage to achieve 90% transition point of the control signal and the VCO frequency to achieve within 470kHz of the final frequency. The time taken to acquire PLL acquisition is governed by the PLL loop filter (C12, C1 and R2) and the crystal oscillator components (XTAL1, C13 and C14). The dominant term for PLL aquistion is the startup time of the crystal oscillator circuit, provided the PLL loop filter settling time is much less than the crystal oscillator startup time. Figure 6 illustrates a suitable test setup for measuring the acquisition time of the PLL. The electrical characterisation parameters are based on the following set of conditions: Crystal Oscillator circuit C13 = C14 = 15pF XTAL 1 Freq. 6.6128 MHz. ESR 15.3 L 85.36 mH C0 1.83 pF C1 6.8 fF PLL loop filter C12 = 1.5 nF, C1 = 180pF R1 = 10K 6. Local oscillator power fed back into 50ohm source at antenna input (RF input). Measured with RF input matching network shown in Figure 11. In-band interference rejection for an unmodulated interfering signal at 100kHz. low side from the wanted modulated signal at 433.92MHz. to achieve a Bit Error Rate =0.01. Figure 5 illustrates a suitable test set-up for measuring the interference rejection and selectivity of the receiver. Wanted signal = (1kB/s. 50% duty cycle) Interfering signal = (unmodulated) -90dBm at 433.92MHz. 2. 3. 4. 5. 7. -76dBm at 433.82MHz. Interference rejection typically equals +14dBm. i.e. in-band interfering signal is 14dBm above the wanted signal level at -90dBm. 8. Actual intermediate frequency determined by choice of crystal and external ceramic filter. 5 KESRX04 Functional Operation Power Down The PD pin, a tristate input, provides a 2 stage power down for the receiver. The receiver is fully operational when the pin is held high and is fully powered down when the pin is taken to ground. Status PD0 PD1 PD2 PD Pin Low (0V) Vcc/2 High (Vcc) Status Receiver powered down Crystal oscillator running Receive mode The AGC circuit comes into operation at input signals greater than ~ -35dBm and reduces the RF amplifer gain by 6dB at an input signal level of ~ -25dBm. Since the AGC operates on the mixer output signal level then the exact point where the AGC comes into operation depends on the RF amplifer to mixer matching circuits and RF amplifer gain. IF interface Unlike KESRX01 there is no internal integrated IF filter. This is to provide a more flexible design and allows the system designer to use a low IF or high IF up to 15MHz. Typically, a 10.7MHz Ceramic IF filter connected between IFOUT and IFIN would be used together with an input RF SAW filter to give very good image channel rejection. The choice of bandwidth for the 10.7MHz ceramic filter depends on frequency tolerancing of the transmitter, receiver, data rate and component cost. The IF filter drive, IFOUT, is a voltage drive with a 300 ohm series resistance. This allows impedance matching to the ceramic IF filter to be set by an external series resistor. A 10.7MHz ceramic filter with, typically, a 300 ohm input impedance does not require an external matching resistor at IFOUT. The input to the log amp, IFIN, is high impedance with an internal 4Kohm shunt resistor. Impedance matching to the output of the ceramic filter is achieved by an external shunt resistor R9 between IFIN and IFDC1. PD0 = Low. None of the receiver circuits are functional. Current, Icc2, is reduced to its lowest level, <50A (Vcc applied). A longer settling time (ts2) is required to restore full performance after switching to receive mode, PD0 to PD2 (Figure 6). PD1 = Vcc/2 or high impedance source (CMOS tristate). A non-receiving state with some critical circuits running including the crystal oscillator. Current consumption, Icc1, is reduced to about 330A. When switching to the receive state, PD1 to PD2 (Figure 6), data can start to be recovered within 1ms (ts3) for signals close to maximum sensitivity. PD2 = High. The receiver is fully functional ready to receive data. Phase Lock Loop VCO The local oscillator (LO) is a VCO locked to a crystal reference by a phase lock loop (PLL). The VCO gain is nominally 40MHz/Volt depending on the external varactor used. The LO frequency is divided by 64 and fed into the phase-frequency detector, where the reference frequency is provided from the crystal oscillator. The phase detector output current into the PLL loop filter is nominally 30A. The max loop filter bandwidth is 50kHz. Conducted LO signals capable of being radiated from the antenna of the complete receiver are suppressed to a level of <-65dBm into 50ohms. RF down-converter An internal RF amplifier is designed to interface to an input SAW filter with a maximum insertion loss of 3dB. The RF amplifier gain is about 13dB at 460MHz when matched into the mixer, while the RF amplifer noise figure is about 4.5dB when fed from a 50 ohm source. The internal RF amplifier is conditionally stable and feeds a double balanced mixer through an external impedance matching circuit, RFOP to MIXIP. The AGC circuit monitors the mixer signal output level. Control is fed back, applying AGC to the RF amplifier to prevent overloading in the mixer and the generation of unwanted distortion products. This also has the effect of reducing the RSSI characteristic slope and extending its range of operation by more than 20dB at high signal levels, compare Figure 9B and Figure 9C. The AGC circuit also applies mixer booster current to improve the linearity of the mixer at high signal levels. This can be confirmed by monitoring the current consumption of the receiver with applied RF signal level Figure 9D. 6 KESRX04 Voltage Controlled Oscillator (VCO) Circuit Design / Layout The Local Oscillator (LO) frequency is controlled by a parallel resonant tuned circuit. The frequency of the local oscillator is controlled by a Phase Locked Loop (PLL), referenced to the crystal frequency. Designing for VCO Track Parasitics To remove the effect of track parasitics the following procedure should be adopted. 1. Open circuit the control feed back from the PLL control loop by removing R1. 2. Connect an external Power Supply Unit (PSU = VCC/2) in place of R1, LF output Figure 3. 3. Using a spectrum analyser, monitor the LO level at the RFin port. Alternatively use a small pick-up coil to loosely couple to the signal generated across L2. 4. Note :- LO level is < -65 dBm, Range = 300 to 500MHz. 5. Vary the value of the PSU input to confirm that there is a corresponding change in LO frequency. Set the PSU at VCC/2. If the VCO does not oscillate at VCC/2, characterise the LO at an alternative voltage. 6. Using a plot of the varactor characteristic determine the varactor capacitance at VCC/2. e.g. for a 2 volt VCC design the Siemens BB833 capacitance at 1Volt = 10pF (approx.). 7. Using the following equation deduce the value of the total stray parasitic capacitance (Cp). Cp = (( 1 ( 2 * LO) 2 * L2 )) -Cv Cv: Varactor capacitance at Vcc/2 8. Using the following equation select the nearest value for L2 to centre the VCO at VCC/2. L2 = 1 ( 2 * LO) * (Cp + Cv ) 2 9. By varying the PSU voltage confirm that the LO is centred correctly at VCC/2, and that the oscillator operates over the range 0 to Vcc. 10. Disconnect the PSU and reconnect R1. Measure the value at LF output using a x10 probe and an oscilloscope. This should be a direct voltage with no ripple at VCC/2 (+/- 0.3 volt). If not repeat steps 1 to 8. To compensate for non standard inductor values vary the value of C18 and C11 to vary the capacitance of the varactor to centre the VCO at VCC/2. Note: It is important to minimise stray capacitance in the VCO circuit to ensure that the VCO starts oscillating. The use of a varactor with a low capacitance at zero bias is advisable. Similarly, reducing the values of C11 and C18 whilst increasing L2 will help to reduce the capacitance of the varactor at 0 volts, improving the reliability of the oscillator. A compact design methodology is recommended for the VCO circuit components L2, C11, C18 and D1. VCO1 (pin 19) C11 R4 L2 C18 VCO Buffer DIV 64 VCO1 (pin 18) D1 Connectfor characterisation RTest (=R1) C12 Phase Detector LF (pin 16) R1 PSU XTAL 1 XTAL1/2 (pins 23/24) C1 R2 KESRX04 Figure 3 Characterising the VCO/PLL operation 7 KESRX04 IF amp/RSSI detector This is a log amplifier with a gain > 80dB and an RSSI output used as the detector. The 3dB bandwidth of the IF log amplifier is typically 20MHz to allow for high IF's to be used. However, normally, this wide IF bandwidth would limit the overall sensitivity of the receiver due to the amplified wide band noise generated in the first IF stage. The RSSI detector is not frequency selective so that any wide band noise introduced after the intermediate filter will be detected as signal. A simple LC noise reduction filter is therefore positioned part way down the log amplifier to reduce the noise power from the earlier stages. Typically this filter only needs to be a fixed component parallel LC filter (L5 // C7) between pins IFFLT1 and IFFLT2 with a 1MHz bandwidth (i.e. Q~10). There is an internal 20Kohm damping resistor across these pins which will determine the Q and the choice of L and C values. Increasing the decay time constant of the AGC circuit by increasing the value of C8 will impair the settling time (time to good data) of the receiver. When duty cycling the operation to the receiver between PD0 and PD2 to lower power consumption of the receiver. When Duty cycling the receiver between PD1 and PD2 the settling time of the receiver is independent of C8. In the application circuit Figure 11 the value of C8 is configured for minimum settling time. Anti-jamming Circuit The output of the RSSI is AC coupled into the Anti-jamming circuit where the signal is DC restored on the peak signal level Figure 7. The coupling capacitor charges to the appropriate DC level which is related to the final slice level for the data comparator. The anti-jamming circuit amplifies the peak of the signal to recover the data signal component even in the presence of CW jamming signals. The interferer causes modulation of the wanted signal at the beat frequency of the two signals and reduces the amplitude of the wanted data component making it more difficult to recover. By-passing the anti-jam circuit Figure 8 will result in data corruption for interfering RF signal levels 6dB below the wanted signal (Figure 5A) The DC restoration circuit has a fast attack time and slow decay time, both controlled by the value of coupling capacitor chosen between RSSI and DETB pins. Figure 5 illustrates a suitable test setup for characterising the interference rejection and selectivity of the receiver. Figure 5A illustrates the in-band interference rejection with the anti-jam circuit connected Figure 7 and by-passed(Figure 8) at 3V Tamb = 25C. Note, the improvement in interference rejection between the two modes of operation over the wanted signal range of -94 to -20dBm. Figure 5B illustrates the difference in receiver selectivity with the ant-jam circuit connected (Figure 7) and by-passed (Figure 8). Note, the improvement in receiver selectivity between the two modes of operation. The selectivity curve with the antijam circuit by-passed is governed by the response of the front end SAW filter, IF ceramic filter and data filter. Providing no rejection for interfering signals within the pass band of the receiver. Whereas the receiver with the anti-jam circuit connected actively responds to the presence of the in-band interfering signal to recover the wanted OOK modulated signal. The action of the anti-jam circuit centres the bandwidth of the receiver around the wanted signal proportional to the data filter bandwidth to suppress the interfering beat frequency. Figures 5A and 5B were recorded with the following component specification. i.e. L= 20000 ; 2. . f IF. Q C= Q 2. . fIF. 20000 An external damping resistor should not be used as this will alter the gain of the log amplifier. A ceramic resonator or filter is not a suitable component here as a low impedance dc path must be maintained to remove dc voltage offsets in the high gain log amplifier. Further improvement in sensitivity can be gained by using a narrow band IF ceramic filter and a narrower noise reduction filter. For a low IF receiver, <1MHz, a low pass filter can be used for both the IF and noise reduction filters. Such a receiver however will have virtually no image rejection capability, and will thus have a 3dB penality in noise factor impairing the ultimate sensitivity of the receiver by a minimum of 3dB. The RSSI output transfer characteristic, at pin RSSI, has a slope of about 16mV/dB. A typical transfer characteristic from RF in input to RSSI output is plotted in Figure 9B, measured with a constant RF input signal. This shows the effect of the AGC in extending the range of the detector to +10dBm RF input signal and includes the effect of the AGC circuit adapting to this signal level. Because the RF amplifier AGC has a fast attack time - slow decay time characteristic the gain of the stage remains constant during the data burst. This means that the change in output for a given extinction ratio also remains constant at approximately 16mV/dB up to peak input signal levels >+10dBm. This requires the decay time constant to exceed the transmitted bit period and no long period of zero signal power has been transmitted. Component Specification (Figure 7) R6 C2 Data Filter BW IFBW SAW BW OOK modulation 130K 270pF 5kHz 470kHz 750kHz 4kB/s (50% duty cycle) Anti-Jam removed (Figure 8) R6 C2 Data Filter BW IF BW SAW BW OOK modulation 12K removed 5kHz 470kHz 750kHz 4kB/S (50% duty cycle) Component specification for Figure 5A and 5B 8 KESRX04 Interference rejection (dB) = Interferer (dBm) - Wanted (dBm) The interference rejection of the receiver for different modulation schemes can be improved by: * Changing the value of C2. Increasing the value of C2 will result in pulse stretching of the recovered signal Adjusting the comparator reference level (DSN) by offsetting the internal reference (Figure 4) by a high value resistor from the DSN pin to Vee and or the peak detector output. (Figure 11). Reducing the bandwidth of the data fillter, intermediate frequency filter and or the noise reduction filter (L5 // C7). Thebandwidth of the receiver must accommodate tolerancing of the data, transmitter and receiver. Increasing the value of AGC capacitor C8 to maintain the level of the AGC control during the "OFF" period of the wanted modulation signal. This will improve the interference rejection of the receiver but increase the time to good data from power-up PD0 to PD2. The application circuit Figure 11 has been optimised for time to good data. i.e. Fc = 5 * 1 ( DataPulsewidth) The output from this filter, DF2, is directly coupled into the inverting input of the data comparator with a fixed slice level applied to the non-inverting input, DSN. A peak detector recovers the signal amplitude on the capacitor. Normally, the comparator reference level used is the internal reference, a capacitor at Pin DSN serving to remove noise pick-up. In order to fine tune the slice level for sensitivity, squelch and optimum interference rejection the slice level can be offset from the internal reference by a high value resistor from the DSN pin to Vee and or the peak detector output (Figure 11). The data comparator (slicer) output, DATOP, is CMOS compatible but is only capable of driving small capacitive loads, <20pF, depending on data rate. Data output has the inverted sense of the input signal at DF2. The output drive current is nominally 30A so that a system using high data rates or higher capacitive loads, e.g. long track lengths, may need to incorporate a buffer transistor to provide the necessary edge speeds to the following logic circuits. The comparator has 20mV hysteresis built-in to reduce edge chatter. The sense of the squelch on the data output is LOW when no signal is present. This may be confusing, as a LOW output during the data burst also corresponds to the `ON' period, i.e. the MARK, of the RF OOK signal. However, it is the very first pulse of the data signal which causes the DC restoration capacitor of the anti-jamming circuit to charge to the correct level appropriate to the final slice level. As a consequence of this the very first pulse of the data transmission may be lost as the receiver adapts to the incoming signal level. * * * Baseband The RSSI output will contain wide band demodulated noise and signals which are within the RF and IF filter pass bands. An additional low pass data filter is therefore used to improve overall sensitivity. KESRX04 has an integrated second-order Sallen-Key data filter whose characteristic is set by R10, R11, C5 and C6. Figure 7 shows the connections and calculation for the -3dB cut-off frequency and filter type, The cut-off frequency is determined from the data rate and the level of pulse distortion which can be tolerated. The data filter cut off frequency is usually set at 3 to 5 times the minimum pulse width period. RFOP MIXIP IFOUT IFIN IFFLT1 IFDC2 IFDC1 RSSI DETB DF0 DF1 IFFLT2 DF2 PEAK DET PEAK VCCRF ANTI-JAM LIM AMP DATA FILTER DATA SLICER DATAOP AGC AGC DIV 64 PFD XTAL OSC LNA DSN 100K Vref RFIN VCO VCO1 PD VCC LF VEERF VCO2 XTAL2 XTAL1 VEE Figure 4 block schematic of KESRX04 9 KESRX04 Pulse Generator 4KB/S (50% Duty Cycle) Variable Delay Line RX CLK OOK Input 433.92 MHz. Signal Generator 1 Wanted Signal KESRX04 PCB N/C N/C RFin RFGND GND Vcc DATA PD N/C Bit Error Rate Trigger Buffer Amplifier RFin Interfering Signal DATA O/P 433.82 MHz. Hydbrid Combiner Oscilloscope DC PSU (3 to 6V) Signal Generator 2 Figure 5 Characterising the selectivityand interference rejection Note : 1 2 3 Variable delay line used to equalise the propagation delay of the receiver. Buffer amplifier used to drive the low impedance input of the Bit Error Ratio analyser. High impedance (*10 probe) oscilloscope probe recommended. Interferer Rejection Ratio 25 20 15 10 5 0 -5 -10 -15 -20 -25 -30 -35 -40 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 Anti-jam circuit connected (dB) Anti-jam circuit By-passed Wanted Signal level (dBm) at 433.92MHz (4kB/s 50% duty cycle) Figure 5a In-band interference rejection of the receiver Note: Unmodulated interfering signal is 100kHz low side from wanted signal. Both signals are within the passband of the receiver (ceramic filter) 10 KESRX04 90 80 70 Selectivity Response (dB) Anti-jam connected 60 50 40 30 20 10 0 -10 -20 431 431.5 432 432.5 433 433.5 434 434.5 435 435.5 436 Frequency Response (MHz.) Anti-jam By-passed Figure 5b KESRX04 selectivity response Note: The action of the anti-jam circuit to centre the bandwidth of the receiver around the wanted modulated signal at 433.92MHz KESRX04 PCB PLL Spectrum Analyser PLL N/C N/C RFin RFGND GND Vcc DATA PD N/C PLL Oscilloscope 1 Power Down Trigger DC PSU (3 to 6V) GND Power Down Switch +/- 470KHz. t Figure 6 Characterising the PLL aquisition time from power-up Note : 1 2 3 4 * * * 5. High impedance (*10 probe) oscilloscope probe recommended Loosely coupled antenna or high impedance FET probe recommended for the spectrum analyser measurement. Time taken for PLL to achieve 90% of final voltage and the VCO within +/- 470kHz. of final frequency (423.33MHz.) Power down switch operation. PD0 = PD pin connected to GND, receiver fully powered down. PD1 = PD pin open circuit or connected to Vcc/2, crystal oscillator running. PD2 = PD pin connected to Vcc, receiver fully operational. Spectrum analyser set to PLL lock frequency (423.33MHz), zero span 470kHz IF bandwidth, t sweep 20mS. 11 KESRX04 C5 R10 C10 C2 R11 C6 RSSI DETB DF0 DF1 DF2 PEAK 100k Sallen Key Sallen-key Data filter Data Filter AMP B RSSI Output Anti-Jam Circuit AMP C DATOP AMP A + SLICER REF DSN 100k Internal Ref. voltage Figure 7 Anti - jamming circuit and data filter Sallen-Key Data filter components c = 2fcY: fc: cut off frequency (Hz) 2.Q R.c 1 2.Q.R.c C5 = C6 = Bessel Q=0.577 Y=1.732 Example Butterworth Q=0.71 Y=1.0 To implement a Bessel response filter with a 10kHz 3dB cut-off frequency, R = 100kohm Bessel Filter Butterworth Filter C5 = 106pF C5 = 150pF C6 = 80pF C6 = 150pF 12 KESRX04 C5 R10 C10 R11 C6 RSSI DETB DF0 DF1 DF2 PEAK C22 100k RSSI Output Anti-Jam Circuit AMP A AMP B DATOP AMP C Sallen Key Sallen-key Datafilter Data Filter REF SLICER R6 100k DSN REF Figure 8 By-passing the anti - jamming circuit 10.7 MHz. 100nF Signal Generator 2 Before Connecting Remove IF Filter KESRX04 PCB IFIN RSSI FET Probe Oscilloscope 1 IFOUT AGC Spectrum Analyser N/C N/C RFin RFGND GND Vcc DATA PD N/C Volt meter 433.92 MHz. Signal Generator 1 Unmodulated Signal A DC PSU (3 to 6V) Figure 9 Characterising the receiver performance (Figure 9A to 9D) Note: 1. 250 Ohms added to signal generator 2 to modifiy its characteristic impedance to mimic the output impedance of the ceramic filter. 2. 100nF capacitor to prevent de-biasing of IFIN. 13 KESRX04 35 30 25 20 Conversion Gain (dB) 15 10 5 0 -5 -10 -15 -20 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 RFIN Unmodulated Carrier at 433.92MHz (dBm) Conversion Gain @ 3V Conversion Gain @ 6V Figure 9a RFIN to IFOUT conversion gain 1.8 1.6 1.4 RSSI Voltage (V) 1.2 Pin 27 RSSI Voltage (V) @ 3V Pin 27 RSSI Voltage (V) @ 6V 1 0.8 0.6 0.4 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 RFIN Unmodulated Carrier at 433.92MHz (dBm) Figure 9b RFIN to RSSI output transfer characteristic See Notes on page 15 14 KESRX04 2 1.8 1.6 1.4 RSSI Voltage (V) 1.2 Pin 27 RSSI Voltage (V)@ 3V Pin 27 RSSI Voltage (V) @ 6V 1 0.8 0.6 0.4 0.2 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 IFIN Unmodulated Carrier at 10.7MHz (dBm) Figure 9c IFIN to RSSI output transfer characteristic 7.7 7.2 6.7 6.2 Current Consumption (mA) 5.7 Current 3V 5.2 Current 6V 4.7 4.2 3.7 3.2 2.7 -100 -80 -60 -40 RFin Unmodulated Carrier at 433.92MHz. (dBm) -20 0 20 Figure 9d Receiver current consumption V s received signal strength RFIN Note: 1. 2. 3. Conversion gain of the receiver is limited by the insertion loss of the front end SAW filter. Dynamic range of RSSI output transfer characteristic (Figure 9B) is governed by the noise figure of the receiver, which is limited by the insertion loss of the front end SAW filter, and the bandwidth of the 10.7MHz ceramic filter. Reduction in conversion gain and increase in receiver current consumption coincides with lift-off of the AGC control line (Pin 12). Action of the AGC applies additional mixer booster current to improve the linearity of the mixer at high signal levels. 15 KESRX04 Figure 10 Applications KESRX04 PCB with 10.7MHz IF Ceramic filter (PCB size = 22mm x 40mm) 16 C7 L5 CF1 C4 1 IFLT1 IFLT2 27 28 C3 KESRX04 I/P GND O/P R9 2 IFDC1 RSSI 26 3 IFIN DETB 25 VCC VCC 1 2 3 C10 R_ON PD 4 IFDC2 PD C25 C14 XTAL1 VCC XTAL1 23 6 IFOUT 22 XTAL2 VCC 7 VCCRF DF0 5 VCC 24 C26 C13 C2 R11 R10 C28 L1 MIXIP DF1 8 21 C23 C15 C20 C6 C29 C9 9 RFOUT DF2 19 20 10 8 7 C5 R4 C11 11 RFIN VCCO2 18 GND GND L4 O/P(GND) O/P 5 1 6 VEERF VCO1 I/P RF_IN 2 L3 L2 C18 12 AGC VEE 16 17 I/P(GND) D1 R1 C12 C8 C16 13 PEAK 15 LF GND C19 4 B3550 3 GND 14 DATAOP DSN C17 C22 RF_IN GND GND VCC DATA PD R3 VCC C1 R2 R6 R7 J1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DATA KESRX04 Figure 11 Applications circuits diagram for KESRX04 with 10.7MHz IF 17 KESRX04 Component list for applications circuit for KESRX04 with 10.7MHz IF (Figure 11) (Not to be used for Test Fixture Circuit Figure 12) Test fixture component values can be supplied on request. Identity C1 C2 C3 C4 C5 C6 C7** C8 C9 C10 C11** C12 C13 C14 C15 C16* C17 C18** C19* C20 C22 C23 C25 C26 C28 C29 R1 R2 R3 R4 R6 R7 R9** R10 R11 R_ON D1 CF1** B355* L1* L2* L3* L4* L5** XTAL1* 433.92 MHz. + SAW 150pF 270pF 10nF 10nF 270pF 270pF 47pF 10nF 56pF 470nF 12pF 1.5nF 18pF 18pF 82pF N/A N/A 12pF 6.8pF N/A 1uF 82pF 82pF 1uF 1uF 82pF 4.7K 10K N/A 4.7K 100K 100K 360 100K 100K N/A BB833 SFE10.7MA26 B3550 39nH 27nH 100nH 33nH 4.7uH 6.61281MHz. Part No Tolerance GRM39C0G151J GRM39C0G271J GRM39X7R103K GRM39X7R103K GRM39SL271J GRM39SL271J GRM39COG470G GRM39Y5V103K GRM39COG560J GRM40Y5V474Z GRM39COG120J GRM39X7R152K GRM39COG180J GRM39COG180J GRM39COG820J N/A N/A GRM39COG120J GRM39COG6R8C N/A GRM40Y5V105Z GRM39COG820J GRM39COG820J GRM40Y5V105Z GRM40Y5V105Z GRM39COG820J N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 4 to 10pF 3dB BW = 470KHz. 3dB BW = 750KHz. LL2012-F39NJ LL2012-F27NJ LL1608-FHR10J LL2012-F33NJ FLU25204R7J +/-100 PPM Supplier Murata Murata Murata Murata Murata Murata Murata Murata Murata Murata Murata Murata Murata Murata Murata N/A N/A Murata Murata N/A Murata Murata Murata Murata Murata Murata Rohm Rohm N/A Rohm Rohm Rohm Rohm Rohm Rohm N/A Siemens Murata Siemens TOKO TOKO TOKO TOKO TOKO Kinseki / Quartz Tek Zarlink Semiconductor Size 0603 0603 0603 0603 0603 0603 0603 0603 0603 0805 0603 0603 0603 0603 0603 N/A N/A 0603 0603 N/A 0805 0603 0603 0805 0805 0603 0603 0603 N/A 0603 0805 0603 0603 0603 0603 N/A SOD323 Radial 5mm2 2012 2012 1608 2012 2520 HC49/4H QP28 KESRX04 KESRX04 KESRX04 *Adjust for alternative centre frequency. **Adjust for alternative IF frequency / ceramic filter. AGC time constant (C8) optimised for minimum settling time (time to good) data N/A. Not Applicable 18 KESRX04 C7 L5 CF1 C4 C3 1 KESRX04 IFLT1 IFLT2 28 I/P GND O/P R9 2 IFDC1 RSSI 27 VCC 3 IFIN DETB 26 C10 Power Down Input 1 2 3 4 C25 C26 VCC 5 IFDC2 PD 25 C14 VCC XTAL1 24 6 VCC 7 IFOUT XTAL2 23 C13 R11 R10 C6 C23 C15 VCCRF DF0 22 Reference Input C28 C29 L1 C9 8 MIXIP DF1 21 C5 9 RFOUT DF2 20 10 VEERF VCO1 19 R4 C11 L2 C18 D1 R1 C12 RF Input (50 Ohm source) C16 11 RFIN VCCO2 18 12 AGC VEE 17 C8 13 PEAK LF 16 14 DATAOP DSN 15 C1 R2 C22 R6 R7 Data Output Figure 12 Production test circuit for KESRX04 with 10.7MHz IF 19 For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. 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Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request. Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE |
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